In March 2025, the Bengaluru (Karnataka) based Indian Space Research Organisation (ISRO) and Chandigarh (Punjab) based Semiconductor Laboratory (SCL) handed over the first production of two 32-bit microprocessors,’VIKRAM3201’ and ‘KALPANA3201’, for space applications.
- These microprocessors were designed and developed by the Thiruvananthapuram (Kerala) based Vikram Sarabhai Space Centre (VSSC) of the ISRO in partnership with the SCL.
- It was handed over to Dr. V. Narayanan, Secretary of the Department of Space (DOS) and Chairman of ISRO, by S. Krishnan, Secretary of the Ministry of Electronics and Information Technology (MeitY) in New Delhi (Delhi).
About VIKRAM3201:
i.Development: VIKRAM3201 is India’s first fully “Make-in-India” 32-bit microprocessor, designed for the extreme environmental conditions of launch vehicles.
- It was fabricated at SCL’s 180 nanometers (nm), Complementary Metal-Oxide-Semiconductor (CMOS) semiconductor facility.
- This processor is an advanced version of the VIKRAM1601, a 16-bit microprocessor that has been used in ISRO’s launch vehicle avionics since 2009.
ii.Technical Features: Both the VIKRAM3201 and the VIKRAM1601 feature a custom Instruction Set Architecture (ISA) with floating-point computation capability and support for the Ada programming language.
- ISRO has also developed software tools such as compilers, assemblers, and an Integrated Development Environment (IDE) in-house.
iii.This is the first of its kind in India and has enabled ‘Atmanirbharata’ in the area of high reliability microprocessors and onboard computers for navigation, guidance & control of launch vehicles.
iv.The initial batch of VIKRAM3201 processors was successfully validated in space during the Mission Management Computer of the Polar Satellite Launch Vehicle (PSLV) Orbital Experimental Module (POEM-4) in the PSLV-C60 mission.
KALPANA3201: SPARC V8 RISC Microprocessor:
i.Kalpana 3201 is a 32-bit microprocessor based on the SPARC V8 (Scalable Processor Architecture, version 8) Reduced Instruction Set Computing (RISC) microprocessor and is based on the IEEE 1754 Instruction Set Architecture.
ii.Designed for compatibility with open-source software toolsets, it has been tested with flight software and is compatible with ISRO’s in-house developed simulators and IDE.
Points to Note:
i.Along with the microprocessors, ISRO and SCL have developed additional devices to miniaturize launch vehicle avionics, including 2 versions of Reconfigurable Data Acquisition Systems (RDAS), Relay Driver Integrated Circuits, and Multi-Channel Low Drop-Out Regulator ICs.
ii.An Memorandum of Understanding (MoU) has been signed between SCL and VSSC for developing miniaturized unsteady pressure sensors for aerodynamic research in wind tunnels.
